Chip designs usually contain gates that have one or more inputs fixed to a logic low level (also called a logical zero level or VSS) or a logic high level (also called a logical one level or VDD). For 90 nanometer and smaller technologies, the fixed inputs cannot be implemented by directly connecting the gate inputs to a power rail or a ground rail. High voltages and currents received from the rails are able to destroy the gates. To protect the gates, additional resistors are connected between the gate inputs and the rails. The resistors are commonly implemented using extra cells connected between the gate inputs and the rails. The newly inserted cells are called “tie-high” cells when connected to a VDD rail, “tie-low” cells when connected to a VSS rail and “tie-to” cells when referred to generically.
Referring to FIG. 1, a block diagram of a conventional tie-low cell 90 is shown. The conventional tie-low cell 90 is used to maintain an input 92 to an example logic gate 94 at the logical low level. The tie-low cell 90 is conventionally implemented as a resistor 96. The resistor 96 may be coupled to a ground rail (i.e., VSS) to generate a signal (i.e., B) at the logical low level. A tie-high cell would generate the signal B at the logical high level.
If the tie-to cells are inserted in a pre-layout netlist, the tie-to cells can cause several problems during cell placement and routing of the design. For example, the tie-to cells can cause the tied gates not to be optimally placed or routed. In particular, some conventional tools are not even allowed to touch such special resistor cells (i.e., the tied-to cells). For the insertion of the tie-to cells after the place-and-route phase of the design, no conventional tool is currently available. Therefore, the tie-to cells are commonly inserted into the design flow by manual netlist changes (i.e., by writing engineering change orders). Manually inserting the tie-to cells later in the flow involves changes to the netlist that are error prone and can lead to non-optimal results